The present invention is directed to a method for processing ATM cells in bidirectional modules processing upstream and downstream data streams in messages, whereby the processing speed is higher than the average cell rate and empty cycles without ATM cells occur in the cell stream.
The present invention is also directed to a module for processing ATM cells in bidirectional, upstream and downstream data streams, for example an OAM module, having inputs and outputs and interfaces for the upstream and the downstream data stream, having an upstream cell processing unit and having a downstream cell processing unit as well as having a processing logic.
ATM, the abbreviation for xe2x80x9cAsynchronous Transfer Modexe2x80x9d, is a network technology that is suitable for the transport of all known signal data such as pure data, voice and video data, etc., whereby the designation ATM is occasionally employed as a synonym for B-ISDN (Broadband Integrated Services Digital Network). A structuring into cells of equal length is characteristic of ATM. The information to be communicated is divided onto ATM cells, namely into packets of 53 bytes, that carry a cell header of 5 bytes and payload information of 48 bytes. The header information thereby identifies a specific virtual connection. By contrast to traditional time-division multiplex methods, wherein time slots are allocated in advance to various types of data traffic, the data traffic incoming at an ATM interface is segmented into said 53-byte cells, and these cells are sequentially forwarded as they were generated. Further details regarding ATM can be derived from the literature. See for example: xe2x80x9cATM-Networks, Concepts, Protocols and Applicationsxe2x80x9d, Handel, Huber and Schroder, Addison-Wesley-Longman, Second Edition, 1994 (ISBN 0-201-42274-3).
Highly integrated circuits in ASIC modules are employed for processing ATM cells. OAM cells are one example, these being utilized for the administration and processing of the OAM streams (OAM=Operation Administration and Maintenance). OAM modules or other cell processing modules are utilized, for example, between network matching units and a switching network module or other modules. FIG. 1 is referenced with respect thereto, this showing a possible architecture. Physical layer modules PHY can be seen at the left and right in the figure, these enabling the transition from a transport network, for example STM1, onto ATM. The dot-dashed lines at the left and right symbolize the boundaries between the physical layer Phy.L and the ATM layer ATM-L. ATM modules BST are provided symmetrically relative to a switching network module SWI, these lying between the switching network module SWI and the physical layer modules PHY. Dependent on the demands and conditions, one or more ATM modules BST can be present. In order to indicate this, a respective ATM module is shown with broken lines.
As can be derived from the block circuit diagram according to FIG. 1, which is relevant both for the prior art as well as for the invention, bidirectional data streams are processed, these being referenced UP for upstream and DOWM for downstream. The designations upstream and downstream indicate the direction xe2x80x9cup toxe2x80x9d the switching network or, xe2x80x9cdown fromxe2x80x9d the switching network given switching networks. Basically, the designations of the two data streams as UP and DOWN, however, are arbitrary and interchangeable with one another.
Separate ATM modules can be employed for the processing of the cells of the two data streams orxe2x80x94as shown in FIG. 1, both data streams can be processed in one ATM module. This is the relevant case here. In the prior art, the gate logic required for the cell processing is thereby doubly implemented in order, namely, to be able to process each of the two data streams.
It is object of the invention to provide a savings in terms of hardware, namely in terms of gate area of the modules, given employment of ATM modules for bidirectional data streams.
This object is inventively achieved in accordance with the present invention in a method for processing ATM cells in bidirectional, upstream and downstream data streams in messages, wherein the processing is performed in modules each having a processing logic at a processing speed higher than an average cell rate, the upstream and downstream data streams having occurrences of empty cycles without ATM cells, in that the processing logic of the modulexe2x80x94for the purpose of an alternating processing of upstream or, downstream cellsxe2x80x94makes upstream and downstream demands for empty cells in order to obtain processing time, the cells of the downstream data stream can be separately backed up and released and, in this way, downstream empty cells can be generated, whereby, given an upstream empty cycle demand in the case of a empty cycle that has occurred, this demand is allowed with priority over a simultaneous downstream demand, and, given a downstream empty cycle demand, a empty cycle is released delayed by a cycle length if an upstream demand is simultaneously present, but is otherwise immediately released.
The object is likewise achieved in accordance with the present invention in a module having a processing logic for processing ATM cells in bidirectional, upstream and downstream data streams in messages, wherein the processing is performed at a processing speed higher than an average cell rate, the upstream and downstream data streams having occurrences of empty cycles without ATM cells, whereby, according to the invention, an empty cycle controller is provided, the processing logic is configuredxe2x80x94for the purpose of an alternating processing of upstream or, respectively, downstream cellsxe2x80x94to send requests for empty cycles to the empty cycle controller, the downstream entry interface is configured to backup and release the cells of the data stream in controlled fashion and, in this way, to generate downstream empty cycles, and the empty cycle controller, which is provided by the entry interface of the upstream data stream with information about occurring upstream empty cycles, is configured, given an upstream empty cycle request, to allow this request with priority over a simultaneous downstream request when an empty cycle occurs, to send an instructionxe2x80x94given a downstream empty cycle requestxe2x80x94to the downstream entry interface for a release delayed by a cycle length when an upstream empty cycle request is simultaneously present but otherwise a command for immediate release.
The present invention utilizes the fact that empty cells having a statistical source occur in ATM systems. Given involvement of a switching network, this is the case in the cell stream UP, namely due to an elevated bit rate, since ATM cells are processed faster in an ATM module than the resupply of ATM cells. There is thus a probability dependent on the input bit rate and on the processing speed in the module that no ATM cell will be located in an input buffer for one of the two cell streams. In the other cell streamxe2x80x94always the xe2x80x9cdownstreamxe2x80x9d cell stream DOWM, for example, below empty cells are actively generated as a result of the backing up of the ATM cells defined by the module, in that no ATM cell is allowed downstream in the input buffer, so that a cell gap, i.e. an empty cell, arises. As a result thereof and by coordinating the empty cells upstream or, downstream, many functions can be processed upstream or, downstream by a single logic in alternation in the cell stream, so that these logic parts need be implemented only once in a module and gate area is saved.
It is expedient when selected functions such as, for example, xe2x80x9cinternal RAM updatexe2x80x9d, are processed in alternation during empty cycles.
Particularly when access to external buffers is difficult, it can be expedient when a backup buffer for the downstream data stream is provided preceding the downstream processing unit, this being controllable by the processing logic via the empty cycle controller.